2009 Presentation at SMTAI San Diego on how and why you need to drive your reflow profile deep within specification. After you watch this 8 min video you will never take profiling for granted again!
To view the complete video series (click here).
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Podcast: Play in new window | Download (Duration: 8:10 — 39.9MB)
What’s wrong with this picture?
Well if you have ever used Kapton tape to attach a thermocouple, you have certainly seen your share of profiles like this!
So what, it is a perfectly good profile, right? Yes, but no. I had a customer who was using KIC’s Navigation (auto prediction) to help create a better “deep in-spec” profile. The only problem, they were trying to optimize on a TC reading that was bouncing literally all over their PCB. Navigator is an awesome tool, but it can only work with what you feed it. If you feed it garbage, it will give you garbage. In their case, it was trying to find them a new solution where literally every time the board was run the bouncing TC that was attached (or I should say was not very well attached) with Kapton was giving false readings. Navigator would give a different solution based on what the TC was reading at that given time. It is like try to put post-it notes on the ocean.
Solution is very simple, eliminate the TC reading from your graph. You can easily do this with the profile you just ran. Look what happens, you go from a far out-of-spec of 126% PWI to a far in-spec of 48% PWI.
So you saved your hard work this time, but you are after all one thermocouple reading short. You added that TC to your profile for a reason. Next go around, do yourself a favor and use a better material for attachment, such a conductive double side aluminum tape, which by the way, a recent study from RIT proves it a superior attachment method aside from sticking to your PCB much better.
I am often asked the question about how to handle components that are close to the outer edge of a PCB. Today a question came in on Circuitnet to highlight this problem:
Title: Issues with BGA Components Near PCB Edges
What issues are we likely to see when we place BGA components very close to PCB edges?
What impact might it have on reliability?
Will equipment (screening, placement, reflow, etc.) require modification?
T. B.
I leave it to the screen printer, pick and place and reflow oven guys to answer the equipment part of the equation, but I can answer how one can determine with a profile if your BGA is getting what it needs as well as how other aspects of your PCB are impacted.
There can be anywhere from a 2 – 5+C variation in temperature across the belt. For example, BTU uses this homemade fixture to test for uniformity. The idea is fairly simple. With a set of type K calibrated thermocouples, you can easily monitor 6 TCs across the belt. You want obviously to see the least amount of variation (if you were wondering the front TC is for measuring air temperature which is also used for automatic mapping of the profile to the oven zones with KIC2000 software).
BGAs typically require more heat to reach their peak temperatures than smaller massed components like electrolytic capacitors. For example, your BGA might have a peak temperature of 245C.
While your electrolytic capacitors cannot tolerate as high as a peak temperature, therefore you want to set their maximum peak temperature lower, for example to 235C (this is just a relative example).
With KIC2000 software, you can define each component in isolation. If the BGA is off on the edge, I might need to bump up even further my peak temperature spec since in many reflow ovens, the outer edge near the rail is the coolest. This is why you see some ovens with heat tape running along the rails! Keep in mind of course as you crank up your oven to reach higher temps to reflow your outer edge BGAs, everything else on your board is also going to be impacted. More the reason you better be hooking up thermocouples to temperature sensitive components to ensure they do not get fried while you are focusing your attention on your BGAs. Profiling software that can “balance” the board is a must. If there ever was a case where software can help solve complex problems in profiling, here you go!
I had a webinar back in July talking about BGA profiling. There is also a video that illustrates what I explained above. You can find this in an earlier posting: http://profilingguru.com/reflow/profiling-bga-webinar/
The Rochester Institute of Technology under the guidance of Dr. S. Manian Ramkumar Ph.D. just conducted (October 2009) the most comprehensive study to date on thermocouple attachment methods. Part I of II was to determine the most accurate and reliable method of thermocouple attachment. Part II that has yet to be released is to determine the best attachment methods for BGAs, with the goal of seeing if there are reliable non-destructive methodologies, so stay tuned.
Aluminum Tape out performed all materials even Kapton! In an ideal word, the best attachment method of a thermocouple to a component is what I like to call a naked TC. Aluminum double sided conductive tape was the closest thing to having nothing at all to attach the thermocouple. Kapton tape is less responsive (deflecting and insulating heat), never mind if you have ever seen a saw-tooth TC plotted on a profile you know it has a very hard time staying in place on your PCB. Additionally, High Temperature Solder which I have always considered the gold standard, is the least accurate or responsive. When you get to the critical peak temperature of your profile, high temperature solder is sluggish to respond to the rapid change in temperatures, thus distorting your readings. As Phil Zarrow and Jim Hall discuss in Board Talk, “mass” on your thermocouple is not your friend. Phil Zarrow:
any measurement method, the key element is to get the thermocouple in good contact with what you are trying to measure and to do it in a way that does not modify the area with a lot of extra mass or material that is going to give you an inaccurate reading….
Bingo! This is actually what this study shows, now with the numbers to back it up.
The study looked at:
The study used a KIC Explorer with standard type K thermocouples. Multiple runs of a substrate coupon (62 mils thick plain copper coated with silver) was routed into 12 uniform 0.24″ isolated sections.
Three identical test coupons were used and run multiple times. KIC’s air-TC was utilized as the control to which each thermocouple was measured as the coupon traveled through all heated zones.
A total of three boards were used, running each board through twice, allowing the internal temperature of the KIC device to drop below 40 degrees C before rerunning the profile.
The tape attach methods were measured uniformly for each RTD connection, using a dial caliper, while the high temperature solder and epoxy quantities for attach were found to be visually uniform.
This graph indicates the mean temperature differential that was noticed within the oven for the various attach methods. The readings are based upon the complete profile starting at room temperature and ending at the peak temperature. The data from the cool down zone was eliminated from the analysis.
The graph shows the mean differential and the 95% confidence interval for each attach method. The Aluminum tape had the least differential (-0.48) followed by Kapton Tape, Loctite Adhesive, CW-2400 and then HT-Solder. The Confidence intervals among most of the attach methods do not overlap except Kapton and Loctite, indicating that the means of the attach methods are significant. Significant differences exist between the methods except between Kapton and Loctite as there is overlap. Clearly Aluminum tape outperforms all of the other methods.
The thermocouples seem to behave similarly within each of the zones of the oven. Zone 6, where the soldering takes place or the peak temperature is reached, the thermocouple attach methods show a much higher temperature than the air temperature, indicating that the PCBs have attained much higher temperatures than the air. A closer examination of ZONE 6 reinforces the selection of Loctite or Aluminum Tape for Phase III of this project.
When considering accuracy, repeatability and responsiveness, Aluminum Tape is a winner. There are of course advantages and disadvantages to each material. For example one can argue you can re profile a PCB set up with high temperature solder, but considering that the mass of the solder distorts your readings, this study even brings into question this bedrock of thermocouple attachment. Never mind high temp solder destroys your PCB as well as there is little control over the size of the blog from TC to TC and board to board. Also don’t forget every time you profile the same board again it loses some mass, which will be the focus of more blogs to come.
Today I came across CM doing exactly this. They were processing networking boards. They were just too complex and expensive to profile, so the solution instead of finding a scrap board or some other reasonable substitute was to profile it as a bare board. I guess the thinking was it is better than nothing, but can anyone honestly say that a bare board comes close to representing a true production board? After all wouldn’t you agree profiling modern boards with mixed components, higher densities and micro-BGAs are already a challenge and to think profiling a bare board would yield any reliable results is a stretch?
So if this is such a terrible solution, what about putting a brick through your reflow oven? A brick, come on Brian, who does this? Well what do you think you are doing when you take one of the many fixtures available on the market that are used for characterizing an oven and using it to profile? I bet if you melted them down (with profiler included) they aren’t far off in mass from a brick. Consider the following attributes of a large mass:
Now notice I included the profiler as part of the mass. Many fixtures further add mass by adding a two pound weight to the fixture! Now don’t get me wrong, these fixture do give you a relative measurement from week to week or month to month as to changes in the oven, but they do not tell you if your product is in spec nor provide a thermal profile. Changes in the oven do not neatly correlate to changes in one’s profile. After all how can they? Chaos theory came out of the field of thermal dynamics, nothing neat about it. Just like a bare board is no substitute to a populated PCB, a brick is also no substitute.
Don’t take my word for it, hear it from the oven manufacturers themselves. http://profilingguru.com/reflow/standard-calibration-tool-for-reflow-process/
Here is a quote from Fred Dimock of BTU:
Oven manufacturers normally use custom designed test fixtures to simulate a board but their real purpose is to measure uniformity across the oven and confirm that the oven is working correctly.
….I have personally seen companies place unrealistic performance specifications on reflow oven testing with (fixtures) boards that have little to do with actual production needs. For example, we once were required to show that an oven could reproduce an inspect ramp soak spike profile on two 12 X 18 inch aluminum sheets that were 0.040 and 0.080 inches thick without changing any recipe parameters….
….From a surface mount manufacturing point of view – single board oven performance testing has little benefit. The real answers are to use actual boards with TCs placed on the critical components….
Both solutions profiling bare boards and bricks are inadequate. Make matters worse if you do both such as I saw with this CM, the results are only compounded. In other words, you are developing a profile based on an unpopulated board and afterwords taking measurements with a thermal mass that does not in anyway represent how your oven will in fact react to a production board. This is classic garbage in, garbage out.
Now there are alternative solutions that don’t require the destruction of a production board in the process. Many of the automated systems will create accurate virtual representations of production boards without the need to attach a single thermocouple. There are also some brilliant software solutions that allow you to create accurate profiles without the need to run a profile. http://profilingguru.com/category/reflow/automation/
There is a great post today in Circuitnet titled “BGA Replacement Limits,” that can be found under Circuitmart. Panelists answer the following question:
How many times can a BGA component be replaced at the same location on the same PCB and retain reliability?
Mark McMeen of STI Electronics suggests that the answer may be as little as two times!
…most companies err on the cautious side and only replace twice at the same location after the initial build which is normally 2 thermal cycles for top and bottomside reflow thermal cycles.
I think a broader question needs to be asked, why are you replacing BGAs in the first place? In my experience, often the answer is due to poor reflow profiling. Often there is nothing wrong with the oven, PCB or BGA. Why is it so hard to properly profile a BGA? I believe the reason is most folks don’t have the option of placing a thermocouple underneath the BGA nor sacrificing a board in drilling a hole on the underside for TC placement. In the old days, you could get away with snaking a TCs under the BGA, but with micro BGAs this is just not an option. So what do people do? They stick a TC on top of the BGA or along side it. Many do nothing at all which is kind of scary and wind up asking question like how many times can I redo my board.
To go to show how hot of topic this is, I held a series of webinars a couple months ago with a turnout in the hundreds. I shared some ideas, here is an abridged 8 min version of the session for those of you that missed it. Part of the answer is proper TC attachment which by the way is currently under study at RIT to see the most reliable method as well as determine if there is a non destructive methods that is both valid and repeatable.
The other part of the equation is profiling your PCB not only for your BGAs but also those components that cannot tolerate as high of temperatures. I’ve seen plenty of manufacturers so focused on a $500 BGA, ignoring pretty much what else is going on with other components on their PCB. Certainly having the ability to define separate specifications, for example a peak temp for a DIP while addressing the special needs of your BGAs will lead to fewer BGAs having to be reworked in the first place.
After all, which is better, to treat the symthoms or the root cause?
RSS feeds, Tweets, blogs and newsletters, how do you keep up? Well here is the latest on what’s available in the SMT industry. I subscribe to all of these newsletters and regularly pick out areas of interest related to profiling for you. I also comb the blogs though I only know of two, not including profilingguru, which is quite remarkable considering other industries have hundreds if not thousands. The SMTA group forum on LinkedIn yields on occasion a nugget, but you need to build a profile to join. SMTnet has always been a jewel. Lastly, Twitter is a new phenomenon for many of us. I am still trying to get the knack of it myself but it does have some value no doubt and will continue to grow.
SMTA on LinkedIn
MB (Marybeth) Allen is interviewed by Philip Stoten of PVP Now at the European Photovoltaic Solar Energy Conference and Exhibition in Hamburg, Germany.
MB shows offs some of the features of the e-Clipse a new way to hold solar wafers without destroying them in the profiling process.
Also MB discusses Spectrum, KIC’s optimization software that is yielding real savings in the Photovoltaic manufacturing industry. A recent published study was discussed in my last blog.
http://profilingguru.com/solar/increasing-silicon-solar-efficiency-manufacturing/
Click here to see the full interview.
What are you paying annually in electricity to run your reflow oven? Not taking into account indirect costs, surcharges, taxes and added wear and tear of running your oven hotter and harder, you might be paying anywhere from $6-8K per line. This number is based off a study conducted at Flextronics Poland, where they pay close to the US national average of $.072 kWh.
Pop Quiz: Can you rank the following in order of impact on lowering your utility bill for your reflow oven?
Well if you are savvy with your utility bill, you probably identified Peak-time Power up Surcharges as the biggest money drain. You probably did not guess Profiling for Energy Savings as the #2 energy savings technique.
Before I take you through all four techniques, keep in mind there are dozens of variables that come into play. The numbers I use for one municipality and/or manufacturer may be vary by location, but the point should not be lost that you can save money and not sacrifice quality production in the process. As an added bonus many of these techniques may also prolong the life of your oven and have other hidden benefits that may impact your operation.
The following represents a fairly typical energy ramp up of a reflow oven from a dead cold state. Many manufacturers will use the default start up to quickly get your reflow oven up to temperature and stabilized for production. Thanks to BTU for providing the following data.
Now compare this to an energy savings ramp up mode for the same oven.
By extending your oven warm up time by only ~15 mins, there is a 15 KW difference in the peak energy output. Many municipalities will charge a monthly surcharge based off of whatever happen to be your peak electricity use over typically a 5-15 min period. So if you happen to turn on all your reflow ovens at the same time, AC, coffee machine, PCs, etc., you are in for a big added surcharge on your utility bill that month.
Potential Savings:
Let’s say you are in South Carolina, Duke Energy charges $13.16 KW as a peak surcharge. Your monthly savings would be $198 per month. Of course if you have more than one oven this savings will be even more significant.
Bonus:
Many smaller manufacturers that perhaps have a single reflow oven, may be close to maxing out on their service. I’ve seen more than one case of a 100 amp facility paying anywhere from $15K – 25K to upgrade to 200 amps. As an example, a 9 zone Heller oven will run at 100 amps at full throttle when heating up, but you can set the oven to heat up in an energy savings mode, knocking your power down to about 63 amps. Suddenly you don’t have to go out and install more service by just making a software change. I know that all the major oven manufacturers that sell to about 80% of the US market (BTU, Heller, Speedline, Vitronics Soltec) have this feature, so check it out.
After 5 years, evidence is pretty conclusive that smart profiling optimization tools can reduce reflow oven energy consumption by as much as 15%. The following three studies demonstrate where power meters were used to measure a “before” profile to an optimized “after” profile, using KIC Navigator-Power or KIC Auto-Focus Power.
There are basically three steps that should not take more than 15 mins to complete:
Step 1: Audit your SMT line speed. You want to determine where is your bottleneck. It is not uncommon to find the reflow oven running faster by 20% or more to the slowest system on your line such as the pick and place or screen printer.
John VanMeter of DG Marketing timing the line
Step 2: Run a profile
KIC Explorer 7 CH
Step 3: Run KIC’s power optimization feature in KIC Navigator. As an process engineer I would set up your minimum allowable conveyor speed in the software above your bottleneck speed. For example, if your current line speed is 30 in/min and an audit reveals your screen printer is running at 20 in/min, set your tolerance in the software to 23 inches. You don’t need to make your reflow oven a possible bottleneck! Lastly, you have the freedom to set the maximum allowable process window index (PWI). In other words, if you know your oven can handle using up to 70% of your available spec, without any drift/variability causing you to go at times out of spec, you know your limit. It really depends on the personality of your reflow oven.
Potential Savings:
Based off the Flextronics Poland study cited above which was conducted on a Heller 1912 EXL manufactured in 2005 and using a kWh rate of $.076 which is practically dead on to the US national average, results in $1062 in annual savings. Which depending on the state of manufacturing can be as high as $2472 annually per oven. 15% savings which was the case at Flex Poland, is not unusual as you will see similar results in the Delta study in Arkansas to be released in October’s issue of Global SMT.
Bonus:
Added features to having KIC’s optimization software Navigator-Power or Auto-Focus-Power are the additional tools you now have for decreasing defects. It is hard for me to know what it costs you each time you send a PCB to rework, the cost of time spent profiling when you should be making on-time deliveries and the stress and aggravation of trying to produce a run of a 100 boards when your customer wants all 100 back! Auto-Focus power allows you to make a very good first guess profile of new board before you even profile! You can find discussions on these tools throughout this blog.
Off-peak hours vary widely per locale. Also depending on the time of year it can vary. Nevertheless, if it is possible to run even a portion of reflow production in off-peak hours your costs kWh can sometimes be half of on-peak prices. I like to use the same rate chart example give above for S. Carolina where Duke Energy charges between 2pm – 6 am, $.0297 kWh vs. $.0563 kWh. Many of us logistically may not have in place a night shift, but most of us can certaintly take advantage of production after 2pm. This is more an issue of smart planning, an exercise in management.
Potential Savings:
If you can schedule a quarter of your production off-peak, and by doing so are able to reduce your rate per kWh by half which is possible in some municipalities your savings could be on the order of $62-74 per month per reflow oven. I came up with this number by again using the Flextronics study as a guide, where they are paying a kWh rate similar to the US national average and shelling out between $5.8K – 7K per year per reflow oven.
By buddy Bob Powledge of DG Marketing out of San Antonio, Texas likes to say, “sure the heck cheaper to blow air than to heat it up!” I agree and there are studies to prove it. Basic physics comes into play. It you can move more heated air over a surface, it will heat up more efficiently and faster. This is why squirrel cages have by and large gotten bigger over the years and other technologies such as static pressure have come about. In one study conducted by BTU who plays around with the idea of static pressure another approach at improving heat transfer rates, the same set-points could increase temperatures by as much as 5C by only changing static pressure. Take this to the next step in our discussion, you can thus REDUCE your oven set-points by that same amount thus reducing electricity usage. Just a word of caution. If you use blowers, you don’t want to crank them up too much unless you like moving components across your PCBs. Many ovens have precision controls for this reason while others offer this as an add on option.
Potential Savings:
I have to take a wild guess in what this translates into dollars since there has not been a study specifically addressing what this means in terms of electricity savings. Considering we have so far been able to build cost models from the profiling studies we can extrapolate some reasonable numbers. In the Delta study, the cumulative setpoint change across their 8 zone Vitronics Soltec oven was 198 C. If you run through each zone, some zones like Z1 there was no change, but when you get to Z5 the delta was 50C! So how do you compare both? If you achieve a 5C reduction across 8 zones or cummulatively 40C and you compare this to our 198C study, this would represent 20% difference. So take our numbers from our profiling study and cut them down to 20%. Remember in the national average example, you could expect $88 in mountly savings per reflow oven, therefore for this example we might see about 20% of that number or $17 per month per reflow oven. I please welcome any oven manufacturer to share the results of a study that questions these assumptions since some guesswork is involved.
Global Solar Technology printed an article on Sept 16, 2009 highlighting an exciting ground breaking study that shows by optimizing the profile during the wafer firing process, a significant gain of .51% is achievable. .51% is HUGE, which can easily translate into hundreds of thousands of dollars in increased revenues per solar manufacturing line. That’s even in today’s depressed silicon market.
(Click here to view full article)
The thermal process of the wafer is one of the keys to achieving improved efficiencies. Drying steps are expected to remove most of the solvent used in the pastes before entering the firing zones. Solar cell metallization generally follows a spike profile type. Wafers only see peak temperature for approximately 1-4 seconds based on wafer and metallization chemistries. The most important steps include the clean burnout of the organics in the paste followed by etching through the silicon nitride (or other) passivation/ARC layer and, ultimately, the formation of good ohmic contact between the sintered silver and the very top layer of n-type silicon. These all lead to low contribution from series resistance and recombination resulting from the formation of the contacts. Control of this profile will become more crucial as the emitter depth decreases with increasing sheet resistance. Both uniformity of diffusion and furnace will be necessary to achieve the desired efficiency improvements.
The article walks you step by step through the study, here is an extend excerpt from the article related to profiling:
The base line profile on these wafers had been developed prior to the project based on extensive knowledge of the paste chemistry and years of practical experience with the metallization process. The base line profile can be seen in dark blue in Figure 1. For the base line test, as with all the subsequent process improvement tests, the wafers were processed at the same time and fired under the same conditions. Ten wafers were run through the furnace within a short period of time, and all were subjected to the same profile. After firing, we measured the cell efficiency in our continuous lamp tester. The average efficiency for the base line profile was 15.53 percent, as can be seen in Figure 2 (η Cell). Based on the type of wafer that was selected for this study, and the fact that a continuous lamp tester was used rather than a flash tester, this efficiency number was considered good. Now we wanted to make it better.
Figure 1: The wafer profiles for each group
It is important to acknowledge that what we were trying to accomplish was not to find a single “golden” profile for the wafers, but rather the optimal thermal process window. The Heraeus paste SOL9235H is a very robust paste that can perform well throughout a range of profiles. Establishing a thermal process window will set the upper and lower limits for the wafer’s peak temperature, time above certain temperature levels, etc. within which the cell efficiencies will be highest.
Figure 2: Cell efficieny testing
Figure 3: Boxplot of cell efficiencies for base wafer profile
Since we did not yet know the upper and lower limits to our process window, we used the base line profile as a starting point, and we initially set relatively wide process limits around it as shown in Figure 4. The profiler software always measures how well the profile fits the chosen process window with a single number called Process Window Index (PWI). The PWI number is 100 percent when the profile is at the edge of the process window. The lower the number, the closer the profile is to the center of the process window. A PWI of 0 percent represents a profile at the very center of the process window.
Figure 4: Original Process Window
Our KIC profiler also has profile simulation software that allowed us to change the furnace zone temperatures or conveyor speed in the software, and to immediately predict the resulting wafer profile. For the first process improvement step, we suspected that a higher peak temperature would benefit the metallization. We tried a few zone temperature changes in the software and studied the software simulation of the corresponding profile before settling on a 10°C increase in the furnace peak zones (Zone 5 and 6). Once the furnace stabilized on the new settings, we ran a set of 10 wafers for our Group 2 test. The average cell efficiency increased from 0.40 to 15.93 percent. For Group 3, we increased the peak temperatures settings in zones 5 and 6 another 10°C, but the average cell efficiency of the 10 wafers dropped by 0.12 percent.
For the Group 4 test, we set the zones back to the Group 2 level and reduced the furnace conveyor speed. The prediction software showed the impact on the wafer profile both in terms of peak temperature changes and, in particular, in terms of time above the various temperature levels shown in Figure 4. Due to this, we reduced the conveyor speed from 200 to 190″/min. The average cell efficiencies increased yet another 0.11 percent above the Group 2 numbers to a cell efficiency of 16.04 percent. Our final test for Group 5 kept the temperatures stable but increased the conveyor speed from 190 to 210″/min. That dropped the average cell efficiency by 0.16 percent.
Figure 5: KIC's e-Clispe TC attachment fixture
Conclusion
By systematically changing certain key profile dimensions, such as peak temperature and time above 500°C, we were able to identify the “sweet spot” in the metallization process. The PWI index and the profiler’s simulation software allowed us to quickly identify the appropriate furnace settings for profiles below, above and in the middle of the optimal settings. This sweet spot yielded an average cell efficiency of 0.51 percent higher than previous experiments had allowed.
The Heraeus SOL 9235H silver paste’s properties allow for high-efficiency processing in a range of profiles, hence a process window can be established around the “ideal” profile identified above. Heraeus now advices its clients to the appropriate process window for each application.
With modern profilers, solar cell manufacturers can adjust their furnace setup until the wafer profile is positioned within the suggested process window. Over time, the thermal process will drift due to a number of variables such as heating lamps changing as they get older, wear and tear in the furnace, conveyor speed drifts, exhaust changes, and more. It then is a simple task for the manufacturing engineer to run another profile, and to use the profiler process optimization software to identify the furnace settings that will yield the appropriate profile.
This method for process optimization depends on accurate and repeatable profile readings. One excessive noise in the profile readings historically has been caused by the attachment method for the TCs. Both cemented and dummy wafer TCs tend to measure the material used to secure the TCs in place, rather than to measure the surface of the wafer. Pinning the TC to the wafer with a weight suffers from non-repeatability. The fixture with flattened TC beads has worked well for us.
Finally, process optimization must be quick and easy enough to be useful for volume production lines, as opposed to only the laboratory line. There is little use in perfecting the process in the laboratory just to see the transfer to the production lines fail because the furnace properties are different. Once the correct process window is established, the high-volume furnaces can be adjusted within minutes, keeping production downtime to a bare minimum. This task must not only be performed during transfer from the lab to the production line, but it also must be performed periodically due to the drift in the thermal process that is a fact of life in any production line. The few minutes it takes to adjust the production furnaces for peak performance is richly rewarded by the ability to consistently produce higher efficiency cells.
Future Studies
The temperature readings taken by the e-Clipse TC attachment fixture are higher than historic readings taken by older TC attachment methods. A future study will focus on quantifying the accuracy and repeatability of the new profiling method as it relates to the theoretical true wafer surface temperatures.
More information: Bjorn Dahle, president of KIC, +1-619-300-5586.
