Increasing Silicon Solar Efficiency Manufacturing

Global Solar Technology printed an article on Sept 16, 2009 highlighting an exciting ground breaking study that shows by optimizing the profile during the wafer firing process, a significant gain of .51% is achievable.  .51% is HUGE, which can easily translate into hundreds of thousands of dollars in increased revenues per solar manufacturing line.  That’s even in today’s depressed silicon market.

(Click here to view full article)

The thermal process of the wafer is one of the keys to achieving improved efficiencies. Drying steps are expected to remove most of the solvent used in the pastes before entering the firing zones. Solar cell metallization generally follows a spike profile type. Wafers only see peak temperature for approximately 1-4 seconds based on wafer and metallization chemistries. The most important steps include the clean burnout of the organics in the paste followed by etching through the silicon nitride (or other) passivation/ARC layer and, ultimately, the formation of good ohmic contact between the sintered silver and the very top layer of n-type silicon. These all lead to low contribution from series resistance and recombination resulting from the formation of the contacts. Control of this profile will become more crucial as the emitter depth decreases with increasing sheet resistance. Both uniformity of diffusion and furnace will be necessary to achieve the desired efficiency improvements.

The article walks you step by step through the study, here is an extend excerpt from the article related to profiling:

The base line profile on these wafers had been developed prior to the project based on extensive knowledge of the paste chemistry and years of practical experience with the metallization process. The base line profile can be seen in dark blue in Figure 1. For the base line test, as with all the subsequent process improvement tests, the wafers were processed at the same time and fired under the same conditions. Ten wafers were run through the furnace within a short period of time, and all were subjected to the same profile. After firing, we measured the cell efficiency in our continuous lamp tester. The average efficiency for the base line profile was 15.53 percent, as can be seen in Figure 2 (η Cell). Based on the type of wafer that was selected for this study, and the fact that a continuous lamp tester was used rather than a flash tester, this efficiency number was considered good. Now we wanted to make it better.

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Figure 1: The wafer profiles for each group

It is important to acknowledge that what we were trying to accomplish was not to find a single “golden” profile for the wafers, but rather the optimal thermal process window. The Heraeus paste SOL9235H is a very robust paste that can perform well throughout a range of profiles. Establishing a thermal process window will set the upper and lower limits for the wafer’s peak temperature, time above certain temperature levels, etc. within which the cell efficiencies will be highest.

Figure 2: Cell efficieny testing

Figure 2: Cell efficieny testing

Figure 3: Boxplot of cell efficiencies for base wafer profile

Figure 3: Boxplot of cell efficiencies for base wafer profile

Since we did not yet know the upper and lower limits to our process window, we used the base line profile as a starting point, and we initially set relatively wide process limits around it as shown in Figure 4. The profiler software always measures how well the profile fits the chosen process window with a single number called Process Window Index (PWI). The PWI number is 100 percent when the profile is at the edge of the process window. The lower the number, the closer the profile is to the center of the process window. A PWI of 0 percent represents a profile at the very center of the process window.

Figure 4: Original Process Window

Figure 4: Original Process Window

Our KIC profiler also has profile simulation software that allowed us to change the furnace zone temperatures or conveyor speed in the software, and to immediately predict the resulting wafer profile. For the first process improvement step, we suspected that a higher peak temperature would benefit the metallization. We tried a few zone temperature changes in the software and studied the software simulation of the corresponding profile before settling on a 10°C increase in the furnace peak zones (Zone 5 and 6). Once the furnace stabilized on the new settings, we ran a set of 10 wafers for our Group 2 test. The average cell efficiency increased from 0.40 to 15.93 percent. For Group 3, we increased the peak temperatures settings in zones 5 and 6 another 10°C, but the average cell efficiency of the 10 wafers dropped by 0.12 percent.

For the Group 4 test, we set the zones back to the Group 2 level and reduced the furnace conveyor speed. The prediction software showed the impact on the wafer profile both in terms of peak temperature changes and, in particular, in terms of time above the various temperature levels shown in Figure 4. Due to this, we reduced the conveyor speed from 200 to 190″/min. The average cell efficiencies increased yet another 0.11 percent above the Group 2 numbers to a cell efficiency of 16.04 percent. Our final test for Group 5 kept the temperatures stable but increased the conveyor speed from 190 to 210″/min. That dropped the average cell efficiency by 0.16 percent.

Figure 5: e-Clispe TC attachment fixture

Figure 5: KIC's e-Clispe TC attachment fixture

Conclusion

By systematically changing certain key profile dimensions, such as peak temperature and time above 500°C, we were able to identify the “sweet spot” in the metallization process. The PWI index and the profiler’s simulation software allowed us to quickly identify the appropriate furnace settings for profiles below, above and in the middle of the optimal settings. This sweet spot yielded an average cell efficiency of 0.51 percent higher than previous experiments had allowed.

The Heraeus SOL 9235H silver paste’s properties allow for high-efficiency processing in a range of profiles, hence a process window can be established around the “ideal” profile identified above. Heraeus now advices its clients to the appropriate process window for each application.

With modern profilers, solar cell manufacturers can adjust their furnace setup until the wafer profile is positioned within the suggested process window. Over time, the thermal process will drift due to a number of variables such as heating lamps changing as they get older, wear and tear in the furnace, conveyor speed drifts, exhaust changes, and more. It then is a simple task for the manufacturing engineer to run another profile, and to use the profiler process optimization software to identify the furnace settings that will yield the appropriate profile.

This method for process optimization depends on accurate and repeatable profile readings. One excessive noise in the profile readings historically has been caused by the attachment method for the TCs. Both cemented and dummy wafer TCs tend to measure the material used to secure the TCs in place, rather than to measure the surface of the wafer. Pinning the TC to the wafer with a weight suffers from non-repeatability. The fixture with flattened TC beads has worked well for us.

Finally, process optimization must be quick and easy enough to be useful for volume production lines, as opposed to only the laboratory line. There is little use in perfecting the process in the laboratory just to see the transfer to the production lines fail because the furnace properties are different. Once the correct process window is established, the high-volume furnaces can be adjusted within minutes, keeping production downtime to a bare minimum. This task must not only be performed during transfer from the lab to the production line, but it also must be performed periodically due to the drift in the thermal process that is a fact of life in any production line. The few minutes it takes to adjust the production furnaces for peak performance is richly rewarded by the ability to consistently produce higher efficiency cells.

Future Studies

The temperature readings taken by the e-Clipse TC attachment fixture are higher than historic readings taken by older TC attachment methods. A future study will focus on quantifying the accuracy and repeatability of the new profiling method as it relates to the theoretical true wafer surface temperatures.

More information: Bjorn Dahle, president of KIC, +1-619-300-5586.

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Save 15% in 15 minutes on your reflow’s energy consumption

Topic: 15% electricity savings in 15 minutes

Save Electricity in 15 mins. R0909B DRAFT

Date: Friday, September 25, 2009
Time: 1:00 pm, Pacific Daylight Time (GMT -07:00, San Francisco)
Meeting Number: 336 789 255
Meeting Password: (This meeting does not require a password.)

To join the online meeting
1. Go to https://kicthermal.webex.com/kicthermal/j.php?ED=107946437&UID=1013415122
2. Enter your name and email address.
3. Enter the meeting password: (This meeting does not require a password.)
4. Click “Join Now”.
5. Follow the instructions that appear on your screen.

Topic: 15% electricity savings in 15 minutes
Date: Friday, September 25, 2009
Time: 1:00 pm, Pacific Daylight Time (GMT -07:00, San Francisco)
Meeting Number: 336 789 255
Meeting Password: (This meeting does not require a password.)

——————————————————-
To join the online meeting

——————————————————-
1. Go to https://kicthermal.webex.com/kicthermal/j.php?ED=107946437&UID=1013415122
2. Enter your name and email address.
3. Enter the meeting password: (This meeting does not require a password.)
4. Click “Join Now”.
5. Follow the instructions that appear on your screen.

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Running lead free and eutectic PCBs simultaneously on the same reflow oven

Surface Mount Technology ran a piece titled Parallel Processes: Simultaneous Lead and Lead-free Soldering with a Single Reflow System written by Hans Bell of Rehm Thermal Systems GmbH.  Hans details a study where by controlling conveyor speed of each lane of a dual-lane system, it is possible to run both a lead and lead free product simultaneously.

The devil of course is always in the details:

Definition of the process window must always be based on the “weakest link,” namely the component with least amount of thermal stability during the soldering process. If two different processes are to be set up next to each other in the same reflow system, and if thermally sensitive components are included on the PCB, great flexibility is required for parameters configuration.

The ability to develop process windows for each product leaving enough room for each to call upon the same oven zone set points is key and of course taking into account special temperature tolerant components on each board.  Hans’ idea is intriguing.  Based on my experience in a world were many PCBs manufacturers struggle to profile or perhaps do not profile at all,  this is certainly a tall order.  Nevertheless his idea is do’able for perhaps many processes, since changing just the conveyor speed to reduce product changeover on a single lane oven is being done today (click here for an excellent application note using KIC product’s to achieve this end).  Why this couldn’t be adopted to a dual lane system running both lead and lead free simultaneously has its merits.

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No Waste: Beyond PCBs in Reflow Profiling

Article is from SMT Magazine

In many situations, EMS providers cannot waste a PCB for thermal profiling. Some ovens are equipped with profiling tools to generate an accurate reflow recipe without thermal profiling. This saves time, labor, money, and materials, but there are limitations.

By Brian O’Leary, KIC

There is a right way and a wrong way to set up a reflow oven to manufacture a new PCB assembly. This article suggests using the wrong method, but for the right reason. If an electronics manufacturer is prevented from following the correct method for setting up the reflow oven for a new production run, does a fallback position exist where they can still expect good results? For example, contract manufacturers find themselves in a not-so-uncommon situation where the manufacturer receives 100 boards and is expected to give a 100 assembled boards back. Sacrificing a single PCB to the profiling process is not an option. In another example, a manufacturer has PCBs that run in the several thousands of dollars. A suitable scrap board is not available for profiling, due to the cost incurred for the lost PCB.

Advantages and Disadvantages of Traditional Reflow Oven Set-up

The traditional method for setting up a reflow oven to manufacture a new PCB assembly is to attach thermocouples (TCs) to the PCB and run a series of profiles. Multiple profiles are usually required for the technician to adjust the oven recipe until an in-spec or deep in-spec profile is found. The introduction of lead-free assemblies has made this task more difficult and time-consuming. However, automatic prediction software and process optimization software have significantly cut down on the number of profile iterations required to determine the oven recipe that provides an in-spec process.

The benefit of this conventional reflow profiling method is clear: It achieves a deep in-spec and therefore stable process that is fundamental to good end-product quality. It also provides documentation to the client that proper process development work was performed.

These procedures, however, tend to sacrifice one or more PCBs. One reason for this concerns the TC attachment method. There are several TC attachment solutions, some more destructive to the PCB assembly than others. The use of high-temperature solder wire is a reliable method, but tends to damage the PCB assembly. Aluminum tape is also a reliable and repeatable method with the added benefit that the tape can be removed after the profile without damaging components.

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A second cause of PCB damage is the fact that each subsequent thermal cycle through the reflow oven raises the risk of latent or real defects as solder joints are re-reflowed, components are exposed to multiple reflow cycles, and the properties of the substrate changing. The PCB gets lighter, discolored, and more brittle with multiple profiles. Therefore, even with non-destructive TC attachment methods, such as aluminum tape, the PCB may need to be discarded when several profiles are run.

A final risk is that the technician selects, often guessing, a wrong initial oven recipe prior to the first profile. The initial recipe could damage the PCB. This could happen when the peak temperature is too high, the slope too steep, the soak prematurely dries out the volatiles in the paste, etc.

Profiling the Reflow Oven, Not the PCB

Modern reflow ovens are a far cry from their legacy siblings. Each oven model produced in volume tends to have very tight and similar thermal characteristics to each other. Equally important, these properties do not change over time as rapidly as in the past due to better flux management, improved oven control systems, more precise mechanics, etc. This enables new thermal process tools that “learn” the behavior of each oven model. To capture the thermal properties of a specific oven model, numerous profiles are run on a variety of PCB assemblies under differing process windows. This database will cover all but the most unusual applications encountered in SMT production. Once this work has been done, it is a simple matter of copying the information onto all the similar oven models. At that point, the operator could simply enter the basic information of the application, such as the length, width, and weight of the PCB assembly as well as the appropriate process window, and the oven will find its suitable recipe (zone temperatures and conveyor speed). This recipe will yield an in-spec profile in the vast majority of the cases without the need to run a profile or attach TCs. Experience with such technologies also suggests that when the recipe generated by the new thermal process tools does not yield an in-spec profile, it is usually very close.

Some U.S. oven manufacturers have completed this work. These reflow oven makers ship ovens with a fully functional database that essentially allows their customers to set up for new production runs without the need for profiling and sacrificing PCBs.

These systems do have limitations. The first was alluded to above, namely that there will be a small percentage of the applications that will not be processed in-spec. The fail-safe method is to wait for the oven to stabilize on the suggested recipe and then run an old-fashioned profile to verify whether it is in-spec. If out of spec, it should, in the vast majority of the cases, be close enough to achieve an in-spec profile on the second try. One profiling pass through the reflow oven, with aluminum tape used for TC attach, should not damage the PCB assembly.

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Another limitation is that an oven will, given enough time, eventually change its thermal properties. Wear and tear, changes in exhaust conditions, preventive maintenance, and a host of other factors will have an accumulative effect on the behavior of the reflow oven. Therefore, the initial database will need to be updated. This can be achieved by running some real-life profiles from time to time, and feeding this fresh information back into the database.

The final limitation is the fact that a system that eliminates profiling, by definition, does not have a profile recorded for the specific assembly. This means that there is no documentation or evidence that the PCB was indeed processed in-spec. Some customers will accept this, while others will not and require reflow profile documentation.

Conclusion

The correct method for reflow oven set up with a new application is to profile the PCB and dial the processed deep in-spec using prediction software. If the electronics manufacturer either cannot or will not perform this task, there are now thermal process tools available that achieve a more than 80% effective solution. Oven-inherent programming produces an in-spec recipe in the vast majority of the situations with no need to profile or sacrifice a circuit board. This technology also saves set up time and associated labor.

Using a profiling technology without an actual PCB profile run is also far better than doing nothing. Many manufacturers in our industry currently do not profile at all, or they limit their profiling to a single application a few times a year. If you do not want to do traditional profiling at all, oven-generated recipes can be an intermediary, rather than blindly reflowing.

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Plugging the Hole in the SMT Reflow Inspection Process

MB (Marybeth) Allen, General Manager of KIC Europe in an interview with Globalsmt.net makes a terrific case for RPI (Reflow Process Inspection). MB_Allen

Here are some excerpts:

Q. 2009 saw the introduction of your RPI In-Line Process Inspection System for SMT reflow ovens.  For manufacturers currently relying on AOI and X-Ray systems to carry out inspection functions, can you explain how this system works and why RPI should be the choice for this process?

Automated inspection systems have become critical in controlling quality throughout the manufacturing process.  SPI (solder paste inspection) and AOI (automated optical inspection) are excellent defect detection tools, within the limitations of their design.  The RPI (reflow process inspection) inspects the reflow process for each and every manufactured PCB.

The quality of a solder joint is not only a function of whether there was adequate solder, accuracy of placement, missing components etc., but that the solder was processed correctly.  For example, the peak temperature needs to be high enough, but not too high to damage the component; the time above liquidous must be within the required range etc.  The AOI machine is not designed to check for these critical events.

KIC’s RPI verifies that the PCBs have been manufactured within the required thermal process window.  Perhaps the best example of where RPI complements AOI is in the soldering of BGAs and other Area Array Packages, where the AOI machine cannot see the solder joints as they are hidden from view by the component body.  RPI even complements X-Ray machines as these inspection systems cannot tell whether the solder joints were processed in accordance with the required profile specs.

Q. So KIC RPI offers both oven and product data in one solution, this obviously enables the operator to harness this key data and use the yield charts to refine the process. What type of data do they receive and how easy is this to understand?

RPI automatically generates both Yield and DPMO (Defects Per Million Opportunities) production charts.  There’s really nothing for the customer to do as the information on all boards produced is captured automatically.  You’ve seen these charts in many factories showing product data for many steps in the manufacturing process.  However, previously data from the reflow process was missing.  Only reflow oven machine data was available.  KIC’s RPI now provides this missing key product process data, providing another key link to product quality.

Q. This product offers a timely solution for manufacturers in this tough climate and I understand it has already received awards for its innovation. What has been your feedback so far?

Yes, RPI has already received several awards around the world.    People are looking for a solution to save money and ensure continued quality control.  When I visit customers and prospective customers their initial questions or requests can be taken care of by using RPI.  It’s wonderful to be able to say “Yes, RPI can help you with that” to most of their requests.  We have plugged the hole in the inspection process.

For the full interview go to: http://www.globalsmt.net/content/view/7583/70/

Awards:

2009 EMAsia Innovation Award in the category of Process Control Software for its RPI in-line inspection system.

2009 NPI Award in the category of Process Control Tools for its RPI in-line inspection system.

Innovative Technology Center Award at Apex 2009

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