Increasing Silicon Solar Efficiency Manufacturing

Global Solar Technology printed an article on Sept 16, 2009 highlighting an exciting ground breaking study that shows by optimizing the profile during the wafer firing process, a significant gain of .51% is achievable.  .51% is HUGE, which can easily translate into hundreds of thousands of dollars in increased revenues per solar manufacturing line.  That’s even in today’s depressed silicon market.

(Click here to view full article)

The thermal process of the wafer is one of the keys to achieving improved efficiencies. Drying steps are expected to remove most of the solvent used in the pastes before entering the firing zones. Solar cell metallization generally follows a spike profile type. Wafers only see peak temperature for approximately 1-4 seconds based on wafer and metallization chemistries. The most important steps include the clean burnout of the organics in the paste followed by etching through the silicon nitride (or other) passivation/ARC layer and, ultimately, the formation of good ohmic contact between the sintered silver and the very top layer of n-type silicon. These all lead to low contribution from series resistance and recombination resulting from the formation of the contacts. Control of this profile will become more crucial as the emitter depth decreases with increasing sheet resistance. Both uniformity of diffusion and furnace will be necessary to achieve the desired efficiency improvements.

The article walks you step by step through the study, here is an extend excerpt from the article related to profiling:

The base line profile on these wafers had been developed prior to the project based on extensive knowledge of the paste chemistry and years of practical experience with the metallization process. The base line profile can be seen in dark blue in Figure 1. For the base line test, as with all the subsequent process improvement tests, the wafers were processed at the same time and fired under the same conditions. Ten wafers were run through the furnace within a short period of time, and all were subjected to the same profile. After firing, we measured the cell efficiency in our continuous lamp tester. The average efficiency for the base line profile was 15.53 percent, as can be seen in Figure 2 (η Cell). Based on the type of wafer that was selected for this study, and the fact that a continuous lamp tester was used rather than a flash tester, this efficiency number was considered good. Now we wanted to make it better.


Figure 1: The wafer profiles for each group

It is important to acknowledge that what we were trying to accomplish was not to find a single “golden” profile for the wafers, but rather the optimal thermal process window. The Heraeus paste SOL9235H is a very robust paste that can perform well throughout a range of profiles. Establishing a thermal process window will set the upper and lower limits for the wafer’s peak temperature, time above certain temperature levels, etc. within which the cell efficiencies will be highest.

Figure 2: Cell efficieny testing

Figure 2: Cell efficieny testing

Figure 3: Boxplot of cell efficiencies for base wafer profile

Figure 3: Boxplot of cell efficiencies for base wafer profile

Since we did not yet know the upper and lower limits to our process window, we used the base line profile as a starting point, and we initially set relatively wide process limits around it as shown in Figure 4. The profiler software always measures how well the profile fits the chosen process window with a single number called Process Window Index (PWI). The PWI number is 100 percent when the profile is at the edge of the process window. The lower the number, the closer the profile is to the center of the process window. A PWI of 0 percent represents a profile at the very center of the process window.

Figure 4: Original Process Window

Figure 4: Original Process Window

Our KIC profiler also has profile simulation software that allowed us to change the furnace zone temperatures or conveyor speed in the software, and to immediately predict the resulting wafer profile. For the first process improvement step, we suspected that a higher peak temperature would benefit the metallization. We tried a few zone temperature changes in the software and studied the software simulation of the corresponding profile before settling on a 10°C increase in the furnace peak zones (Zone 5 and 6). Once the furnace stabilized on the new settings, we ran a set of 10 wafers for our Group 2 test. The average cell efficiency increased from 0.40 to 15.93 percent. For Group 3, we increased the peak temperatures settings in zones 5 and 6 another 10°C, but the average cell efficiency of the 10 wafers dropped by 0.12 percent.

For the Group 4 test, we set the zones back to the Group 2 level and reduced the furnace conveyor speed. The prediction software showed the impact on the wafer profile both in terms of peak temperature changes and, in particular, in terms of time above the various temperature levels shown in Figure 4. Due to this, we reduced the conveyor speed from 200 to 190″/min. The average cell efficiencies increased yet another 0.11 percent above the Group 2 numbers to a cell efficiency of 16.04 percent. Our final test for Group 5 kept the temperatures stable but increased the conveyor speed from 190 to 210″/min. That dropped the average cell efficiency by 0.16 percent.

Figure 5: e-Clispe TC attachment fixture

Figure 5: KIC's e-Clispe TC attachment fixture


By systematically changing certain key profile dimensions, such as peak temperature and time above 500°C, we were able to identify the “sweet spot” in the metallization process. The PWI index and the profiler’s simulation software allowed us to quickly identify the appropriate furnace settings for profiles below, above and in the middle of the optimal settings. This sweet spot yielded an average cell efficiency of 0.51 percent higher than previous experiments had allowed.

The Heraeus SOL 9235H silver paste’s properties allow for high-efficiency processing in a range of profiles, hence a process window can be established around the “ideal” profile identified above. Heraeus now advices its clients to the appropriate process window for each application.

With modern profilers, solar cell manufacturers can adjust their furnace setup until the wafer profile is positioned within the suggested process window. Over time, the thermal process will drift due to a number of variables such as heating lamps changing as they get older, wear and tear in the furnace, conveyor speed drifts, exhaust changes, and more. It then is a simple task for the manufacturing engineer to run another profile, and to use the profiler process optimization software to identify the furnace settings that will yield the appropriate profile.

This method for process optimization depends on accurate and repeatable profile readings. One excessive noise in the profile readings historically has been caused by the attachment method for the TCs. Both cemented and dummy wafer TCs tend to measure the material used to secure the TCs in place, rather than to measure the surface of the wafer. Pinning the TC to the wafer with a weight suffers from non-repeatability. The fixture with flattened TC beads has worked well for us.

Finally, process optimization must be quick and easy enough to be useful for volume production lines, as opposed to only the laboratory line. There is little use in perfecting the process in the laboratory just to see the transfer to the production lines fail because the furnace properties are different. Once the correct process window is established, the high-volume furnaces can be adjusted within minutes, keeping production downtime to a bare minimum. This task must not only be performed during transfer from the lab to the production line, but it also must be performed periodically due to the drift in the thermal process that is a fact of life in any production line. The few minutes it takes to adjust the production furnaces for peak performance is richly rewarded by the ability to consistently produce higher efficiency cells.

Future Studies

The temperature readings taken by the e-Clipse TC attachment fixture are higher than historic readings taken by older TC attachment methods. A future study will focus on quantifying the accuracy and repeatability of the new profiling method as it relates to the theoretical true wafer surface temperatures.

More information: Bjorn Dahle, president of KIC, +1-619-300-5586.


Thermocouple Attachment Discussion

Phil Zarrow and Jim Hall of ITM Consulting have a very good piece on TC attachment on Board Talk hosted by

In their first session, they talk about permanent TC attachment, such as high temp solder and epoxy (click here for a link to their recording).  Yours truly left a comment with the boys:

We are a big fan of conductive Aluminum tape, used along with Kapton for strain relief like you mention in your podcast. We talk about high temp solder and epoxy which can work also, but like you said you got to be careful of mass. Lot of times we see unequal amounts applied per TC that can throw your readings. What is your take on aluminum tape, realizing of course it is a non permanent solution?

Well, they came back with a terrific response (click here for a link to their recording), where they make a clear distinction between destructive vs. non destructive methods.  Non destructive methods are often the only option, since customers cannot sacrifice a board for profiling.

Phil goes on to say:

any measurement method, the key element is to get the thermocouple in good contact with what you are trying to measure and to do it in a way that does not modify the area with a lot of extra mass or material that is going to give you an inaccurate reading….

Phil talks about using for example Kapton as a strain relief to ensure there are no stresses on the point of TC attachment.  I’ve been saying for years to use techniques such as window paning where you apply Kapton around the boarder of your aluminum tape to help keep your TC secure if profiling more than once the same PCB.  Make sure not to put Kapton over the bead since Kapton can behave as an insulator.

I think Phil makes a great point on emphasizing the “size” of the tape you are using.  Again you don’t want the material’s mass to become an issue.  So the name of the game is don’t go overboard.  Personally I prefer a 1/4″ square piece of aluminum tape along with 1/4″ Kapton.

Jim Hall makes also an excellent point that the same goes for “destructive” methods when using high temp solder and epoxy.  You don’t want to overdo it, or the mass can effect your readings.   I would add further that you need to be very careful that the mass be equal from TC to TC.   It has been my long held belief that the blob of epoxy or solder if of unequal amounts TC to TC, PCB set up to PCB set up will add variability into your process.  Just keep your materials to a minimum to get the job done.

Many of these assertions are currently under review by an RIT study.  Hope to have results as early as the end of this month.  KIC conducted a study 10 years ago on all the materials mentioned (click here for the report).  Since a decade has past, one could assume materials have improved therefore warranting a second look.  Stay tuned!


Non Destructive BGA Profiling Test #1

I am currently investigating a non destructive method of BGA profiling that is reliable.  Here are the results of my first test.

Set Up:

Four thermocouples are attached to the same BGA (TOP, SIDE, INSIDE and BOTTOM surface), as pictured below.  Conductive aluminium double sided tape is used along with Kapton.  A KIC Explorer is the profiler.

To see more on Thermocouple attachment visit my post:

A hole was drilled out to attach the INSIDE TC.




Two tests were run, the first was running the board on the belt followed by running the same board on the chain/tab conveyor.


As you can see the delta for ramp and peak is the greatest, while soak is minimal.  The inside TC runs the hottest and the underside bottom TC follows fairly closely the behavior of the inside TC.


This second profile was run on the belt with the same board but for a different BGA.   Again we see similar behavior, where the INSIDE and BOTTOM TCs exhibit similar behavior.


This third profile was running the same board and same BGA as in the second example but this time on the chain/tab.   Interestingly, all TCs were a good predictor of the INSIDE TC except when getting to the cooling zone.  The BOTTOM TC was only a good predictor of the INSIDE TC.


Profiling BGA Webinar

Profiling BGA Webinar Supplemental (July 1, 2009):

Component Specific Specs

We discussed the need to define BGA specs separate from other components that have different reflow requirements.   BGAs typically require more heat to reflow properly but typically there are many other “smaller” components that also populate a PCB that will overheat if you develop your process solely around the BGA.   The following 2:40 min video reviews how you can bring both your BGAs and other temperature sensitive components into spec, striking a thermal balance that results in quality products.

Thermocouple Attachment

The following 1 min video shows one of the most reliable direct methods of TC attachment for BGA profiling.

…..but, who can always sacrifice a PCB in the process?   We talked about some indirect/non-destructive methods for profiling BGAs that are suggestive, but inconclusive.   In the fall I hope to have some results of a study that will help our industry come up with solutions that one can reasonably predict the temperature/profile of a BGA without destroying the PCB in the process or worse the BGA!

BGA Inspection

First there was SPI (solder paste inspection), then there was AOI, now there is RPI (Reflow Process Inspection)


You can see a prior blog posting discussing RPI at:

RPI works in the world of continuous reflow monitoring, where a profile is created for each and every production board.

In order to automate reflow profiling, a baseline/virtual profile is first established, where one runs a traditional profile with PCB, TC attachment and profiler while the on-board system of 30 thermocouples gathers the same profiling data and reconstructs and converts the traditional profile to a virtual representation. Once a virtual profile has been established, profiles can be collected for all production boards.  SPC charting, cPk, traceability and process control are all possible.

So rather then the reflow process being a black box, where anything and everthing can go wrong…..

illustration_5….alternatively, do you not only know what is going on continuously, but your BGAs using the techniques above are being monitored on a continuous basis.


Your Questions:

Q: Doesn’t the thermocouples utilized by the oven itself (assuming that they are calibrated and verified) provide the same basic information as the secondary set of TCs you are referring to?

ANSWER:  No, the oven thermocouples and the secondary KIC  TCs have completely different and separate functions.  The oven TCs are typically located close to the heaters since their job is to turn the heaters on and off as the temperature drifts from the set points.  The KIC 24/7 (or KIC Vision) TCs, located along the conveyor, help to automatically measure the profile that each PCB experiences as it is processed through the reflow oven or wave solder machine.  This function is called Virtual Profiling.

Virtual Profiling (VP) provides process traceability as it logs the profile for each PCB, along with information on how this profile fits the established process window.  The VP works in real time and offers instant alarm when the process (profile) drifts out of spec.   Because it provides basic SPC charting, it acts as an early warning system for trouble ahead.  Think of the KIC24/7 or KIC Vision as an automatic profiling system in real time.

Q:  I encountered wetting issue with CSP and BGA, how do I solve them?   /   Q: How about wetting issue?

Answer; In some cases, but of course not all cases, wetting issues are a result of incomplete flux activation in the solder paste and an overall low temp soak, where the components did not reach sufficient energy levels before entering the reflow, TAL stage of the process. Many of these issues are related to Pb – free solder pastes, mixed RoHS components or a number of other variables.

I suggest that the best answer is to research the publications available on the Web for the most relevant solution. The following is a link that closely resembles the issue, but again, you will need to research the most relevant to your situation.

Q:  How do you take measurements on each board without TCs?

Answer: KIC software algorithms compare what was observed at the time of the Baseline Profile to what is present within the oven during production. Using the 30 thermocouples in the oven, this data is communicated to the eTPU and the output is the PWI based on the specific process and the specification of that process.

Q:  How well does the DPMO relate to the actual defect where there could be placement defects interacting with reflow?

Answer: DPMO is a parameter of only the thermal reflow process. If issues exist in placement or screen printing, it will not be reflected in the DPMO, since KIC is only monitoring the thermal process. Given that all other aspects of the SMT line is functioning properly, DPMO will give an assessment of the thermal defects assuming that the proper solder paste and placement is present at the time the product enters the oven.

Q:  What about paste formulations?

Answer: KIC works with any solder paste manufactures to build the solder paste library that is present in the KIC software. This library is updated periodically and verified by the solder paste manufactures in most instances. The library however does not at any one time contain all information about all possible solder pastes. We try our best to be certain the information is present, but changes in formulation and engineering at the solder pate manufactures sometimes causes gaps that are beyond our control.

Q: How important is it to drill into the BGA ball and put the TC in it, vs. putting on the package, slip under the package, and on the bottom side of the board?

Answer: There are many variables in PCB design and component placement that directly and indirectly affect other components, in this case BGA. The best possible answer to this question is in the amount of data that is collected, how it is collected and how this information is applied to the specific PCB and BGA directly. Gathering as much information as possible, charting this info and drawing data driven values is the best possible formula for successful BGA reflow. Using all available data collection methods and positions aids in successfully reflowing this package.

As indicated during the webinar, we are currently commissioning a study to see if non destructive methods can be used in place of drill a hole.

Q: Does your software always choose an extended peak recipe?

Answer: No. Based on the type of recipe and profiles that are part of your normal production determines what path the KIC Navigator (auto-prediction) directs the profile. If your profiles are mainly RTP, the software looks at the values of the library data and suggests set points that will lead to a RTS profile. If your profiles are largely RSS, then the suggested set points will tend towards a RSS profile.


Soldering and Profiling Discussion Panel at Apex 2009

Panelists at APEX discuss misconceptions about the reflow process and how to Minimize Delta Ts, etc.

Mike Buetow of Circuits Assembly magazine moderates a discussion panel on soldering and thermal profiling at APEX 2009. Panelists include Keith Howell of Nihon Superior, Fred Dimock of BTU and Michael Limberg from KIC.

Much of the 30 min discussion hits upon how customers often confuse an oven’s recipe with a PCB’s profile/recipe.  Factors such as density, delta Ts, belt speed, different components and extraction are used as examples as to why the oven’s set points don’t always match the temperatures on the PCB. All panelists agree that a fair amount of customers do not understand these important concepts.

Fred Dimock of BTU cites an interesting study he conducted to highlight the difference mass has on the peak temperatures a board experiences without changing the oven set points. The example he gives is a 100gram board that achieves a 231 C peak when compared with a 230gram board only reaching a 225C peak with everything else being equal. Panelists agree that customers often expect to see the same profile at a given oven set up, when obviously factors such as mass play such a critical role!

All panelists talked at length about how to minimize delta Ts as an important factor in producing quality PCBs.  The PCB design and layout of components was discussed by Keith and Mike.

Fred cited a study that higher convection rates also yield a lower delta T, taking into account the need to maintain a stable environment early on in the reflow process before components have had a chance to take hold. Starting at low convection allowing the flux to become tacky (thus keeping components in position) and eventually raising convection in the peak zone can minimize large deltas.

Fred also shared a profiling trick with Ramp Soak Spike profiles he likes to use when trying to minimize the delta Ts at peak.   In RSS profiles, one would run as close to the edge of the top of the spec of soak and get as high as you can in temp early before you hit the spike, but you need a quality profiler and good ThermoCouple attachment to pull this off, Fred added.

The session also covered briefly upon topics such as:

  • Vapor Phase profiling: Keith & Mike
  • Nihon’s SN100C paste: Keith
  • How to Profile Expensive Components: Mike
  • Importance of Cool Down and considerations, such as the roll of large BGAs: Fred and Keith

To watch a video of the session, click here: